Senior DFT Engineer – AI-Driven ASIC for LEO Satcom

Amazon Kuiper Manufacturing Enterprises LLC; San Diego (CA); Presencial; USD 185.000 - 250.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health insurance

401(k) matching

Paid time off

Parental leave

Descripción de la vacante

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced DFT Engineer to define and implement DFT for high-speed CMOS chips used in LEO satellite communications. You will collaborate with ASIC teams across sites to embed MBIST, clock controls and JTAG, while optimizing fault coverage with RFIC partners.

The role emphasizes automation, AI-enabled DFT workflows and adherence to timing and power targets as products move toward silicon bring-up.

Formación

• Bachelor's degree in Electrical/Communications Engineering or equivalent experience in electrical engineering.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT insertion and validation.

Responsabilidades

• Architect and define DFT solutions adapted to the specific use of various LEO chips.
• Contribute to IPs and DFT methodology while embracing AI flow.
• Collaborate with ASIC design teams to integrate DFT logic (MBIST, clock controls, JTAG).
• Coordinate with RFIC teams to ensure high fault coverage on RF blocks.
• Ensure blocks meet DFT, timing and power targets with the implementation team.
• Translate ATE patterns to tester formats with Test Engineering.
• Assist in bringing up digital portions of LEO chips with Test team.

Conocimientos

DFT techniques

Automated DFT scripting

AI/ML for DFT flow

RFIC collaboration

Educación

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D in Electrical / Communications Engineering

Herramientas

MBIST

Clock controls

Descripción del empleo

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced DFT Engineer to define and implement DFT for high-speed CMOS chips used in LEO satellite communications. You will collaborate with ASIC teams across sites to embed MBIST, clock controls and JTAG, while optimizing fault coverage with RFIC partners.

The role emphasizes automation, AI-enabled DFT workflows and adherence to timing and power targets as products move toward silicon bring-up.