Senior DFM Engineer: Yield & Verification Lead

Samsung Electronics; Austin (TX); On-site; USD 106,000 - 145,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Life insurance and 401(k) matching

Onsite café and fitness facilities

Paid maternity and paternity leave

PTO + 2 holidays and 10 holidays

Job summary

Samsung Austin Semiconductor is hiring a Design for Manufacturability (DFM) engineer to drive verification, tech transfer, and process margin improvements for 300mm wafer nodes.

The role requires strong scripting, Cadence Virtuoso, and knowledge of mask workflows, with a focus on delivering reliable high-volume production outcomes and close collaboration with design and fabrication teams.

Qualifications

• Bachelor’s/Master’s/PhD in Electrical Engineering or related field; strong verification background.
• Experience with design verification processes and performance analysis.

Responsibilities

• Collaborate with internal teams and customers to develop new device offerings and libraries.
• Lead design risk assessments for new product introductions and yield improvement initiatives.
• Use EDA tools to analyze designs, extract netlists, run timing analysis, and provide guidance to fabrication teams.

Skills

Scripting

Design verification

Yield analysis

Education

Electrical Engineering degree (B.S./M.S./Ph.D.)

Tools

Cadence Virtuoso

ICC2/TCAD

Calibre

YieldExplorer

StarRC/xRC

GDSII

Job description

Samsung Austin Semiconductor is hiring a Design for Manufacturability (DFM) engineer to drive verification, tech transfer, and process margin improvements for 300mm wafer nodes.

The role requires strong scripting, Cadence Virtuoso, and knowledge of mask workflows, with a focus on delivering reliable high-volume production outcomes and close collaboration with design and fabrication teams.