Senior DFM Engineer - Advanced Node Verification

Samsung Electronics Perú; Austin (TX); On-site; USD 106,000 - 145,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Life Insurance

401(k) matching

Onsite facilities

Paid time off

Personal holidays

Wellness incentives

MBO bonuses

Job summary

Samsung Austin Semiconductor is seeking a Design for Manufacturability (DFM) engineer to provide design verification for high‑volume production, optimize yields, and support new product introductions on advanced nodes.

The role involves collaboration with internal and customer design teams, EDA tool usage, SVRF/TCL coding, scripting for automation, and presenting results to leadership. Experience with 300mm/16nm–10nm nodes is preferred.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering.
• Other engineering domains acceptable if candidate has design verification experience.
• Experience with Cadence Virtuoso or other EDA tools in at least one listed suite.

Responsibilities

• Collaborate with internal and customer design teams to develop new device offerings and libraries.
• Lead design risk assessment for new product introductions and yield/margin improvements.
• Use EDA software to extract netlists, perform timing analysis, and guide fabrication for margin improvements.
• Develop solutions/methodologies to fix future vulnerabilities in designs.
• Write SVRF/TCL code for design risk assessment and automate workflows with scripting.
• Present technical updates to senior leadership and other stakeholders.

Skills

EDA tools experience

Scripting (Python/TCL/Shell)

Education

Bachelors/Masters/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Calibre/StarRC/xRC/ICC2/TCAD

Job description

Samsung Austin Semiconductor is seeking a Design for Manufacturability (DFM) engineer to provide design verification for high‑volume production, optimize yields, and support new product introductions on advanced nodes.

The role involves collaboration with internal and customer design teams, EDA tool usage, SVRF/TCL coding, scripting for automation, and presenting results to leadership. Experience with 300mm/16nm–10nm nodes is preferred.