Senior DFM Engineer: Drive Yield & Innovation in Tech

Samsung Semiconductor; Austin (TX); On-site; USD 106,000 - 145,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k) matching

Onsite facilities

Job summary

Samsung Austin Semiconductor is seeking a DFM engineer to provide design verification for high-volume production and optimize new products introduced at Samsung Austin Semiconductor. You will collaborate across internal and customer design teams to deliver robust device libraries and improve design margin.

The role requires expertise with Cadence Virtuoso and other EDA tools, strong scripting skills, and a solid understanding of the design-to-mask workflow.

Qualifications

• Bachelor's/Master's/PhD in Electrical Engineering or related field with design verification experience.
• Experience with Cadence Virtuoso or other EDA tools (Calibre, Yield Explorer, StarRC/xRC, ICC2, TCAD).
• Working knowledge of the design-to-mask workflow (schematic, simulation, layout, physical verification, GDSII).
• Experience with 300mm 16nm/14nm/10nm nodes wafer manufacturing is preferred.
• Strong scripting experience in Tcl, Bash/Shell or Python.

Responsibilities

• Collaborate with internal teams and customers' design teams to develop new device offerings, pcell and standard cell libraries.
• Lead projects on design risk assessment for new product introductions and yield improvements.
• Use EDA software to analyze and design, extract netlists, run timing analysis and guide fabrication on margin improvements.
• Lead/participate in devising solutions to fix future design vulnerabilities.

Skills

Scripting (Python/Bash/Tcl)

Education

Electrical Engineering degree (Bachelors/Masters/PhD)

Tools

Cadence Virtuoso

Calibre

Yield Explorer

StarRC/xRC

ICC2

TCAD

Job description

Samsung Austin Semiconductor is seeking a DFM engineer to provide design verification for high-volume production and optimize new products introduced at Samsung Austin Semiconductor. You will collaborate across internal and customer design teams to deliver robust device libraries and improve design margin.

The role requires expertise with Cadence Virtuoso and other EDA tools, strong scripting skills, and a solid understanding of the design-to-mask workflow.