Senior DFT Design Architect – End-to-End Silicon

Samsung Electronics; United States; Remote; USD 150,000 - 210,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) in Bangalore seeks a senior DFT/MBIST expert with 12–20 years of experience to drive end-to-end DFT efforts, from concept to silicon bring up, across RTL and physical integration.

The role emphasizes strong fundamentals in scan architectures, cross-functional collaboration, and hands-on verification, SDC development, and post-silicon issue debugging to ensure high reliability and yield.

Qualifications

• Preferably 12 to 20 years of relevant experience with exposure on end-to-end activities on DFT (Concept, implementation to silicon bring up)
• Strong fundamentals on Scan Architectures, MBIST Architectures and Custom BIST
• Hands-on experience on Implementation, Verification scenario development, testbench coding, Verification at various abstractions (RTL, GLS with UD and SDF)
• Hands-on experience on SDC development
• Exposure to post-silicon issue debug
• Good problem solving skills
• Experience in working with cross-functional teams.
• Attention to details, quality reviews and resk management

Responsibilities

• Lead end-to-end DFT activities from concept to silicon bring up
• Apply scan architectures, MBIST architectures and custom BIST
• Develop implementation and verification scenarios, build testbenches and verify across RTL and GLS with UD and SDF
• Develop SDC constraints and timelines
• Engage in post-silicon issue debugging
• Collaborate with cross-functional teams to ensure design quality

Skills

DFT concepts

MBIST architectures

Custom BIST

Verification

Testbench coding

SDC development

Post-silicon debugging

Cross-functional teamwork

Attention to detail

Education

B.Tech/B.E

M.Tech/M.E

Tools

RTL

GLS

SDF

Job description

Samsung Semiconductor India Research (SSIR) in Bangalore seeks a senior DFT/MBIST expert with 12–20 years of experience to drive end-to-end DFT efforts, from concept to silicon bring up, across RTL and physical integration.

The role emphasizes strong fundamentals in scan architectures, cross-functional collaboration, and hands-on verification, SDC development, and post-silicon issue debugging to ensure high reliability and yield.