Senior Design Verification Engineer – SoC/ARM Expert

Value Innovation Labs; San Jose (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

Value Innovation Labs is seeking a Senior Design Verification Engineer for on-site work in San Jose, CA. You will lead end-to-end verification for IP, Subsystems, or SoC projects, owning technical aspects and collaborating with design, architecture, and customer teams.

The role requires 6+ years of DV experience, strong SystemVerilog/UVM, C/C++, and HVL skills, plus knowledge of ARM cores and verification methodologies. Travel to customer sites may be needed.

Qualifications

• BE / BTech / MTech in Electronics, Electrical, or related discipline

Responsibilities

• Design verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express.
• Strong in HVL (UVM / SystemVerilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flow.
• Strong in constraint random verification, assertion writing, coverage analysis, debugging.
• Familiarity with ARM cores, formal verification, SV DPI-C is a plus.
• Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus.
• Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plus.
• Must be a team player with good oral and written communication skill.
• Self-motivated with the ability to work independently and interface effectively with engineers across divisions and remote location.

Skills

SystemVerilog

UVM

C/C++

Perl

TCL scripting

Assertion writing

Coverage analysis

AMS/Low Power verification

ARM cores

Education

BE/BTech/MTech in Electronics or Electrical

Tools

EDA tools

SV DPI-C

Job description

Value Innovation Labs is seeking a Senior Design Verification Engineer for on-site work in San Jose, CA. You will lead end-to-end verification for IP, Subsystems, or SoC projects, owning technical aspects and collaborating with design, architecture, and customer teams.

The role requires 6+ years of DV experience, strong SystemVerilog/UVM, C/C++, and HVL skills, plus knowledge of ARM cores and verification methodologies. Travel to customer sites may be needed.