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Centraprise is seeking an experienced Design Verification Engineer to verify complex SoC designs, focusing on ARM-based processors and AMBA protocols. The role emphasizes SystemVerilog and UVM-based verification environments, with heavy debugging and cross-team collaboration.
You will develop testbenches, test plans, and coverage models, and drive verification closure through analysis of results. This contract/full-time position is based in Austin, TX and Bay Area, CA with on-site expectations.
Location: Austin, TX / Bay Area, CA
Job Type: Contract / Full-Time
We are looking for an experienced Design Verification Engineer with strong expertise in SoC verification, SystemVerilog, and UVM. The ideal candidate should have hands-on experience verifying ARM-based processors and working with AMBA protocols.
Experience with High-Speed I/O interfaces, such as: