Senior Verification Engineer (PCIe & SV/UVM)

Credo; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Medical benefits

Job summary

Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You’ll develop verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.

The base salary range is 130,000 - 160,000 USD per year with discretionary bonus, equity, and a full range of medical and other benefits.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of RTL and functional verification using SV/UVM.
• PCIe verification experience.
• Experience with gate-level simulation and firmware-based simulation.
• Proficiency in RTL design and computer architecture concepts.
• Strong debugging, problem-solving, and analytical skills.
• Effective collaborator who thrives in cross-functional teams.

Responsibilities

• Understand design intent and develop comprehensive verification & test plans.
• Develop reusable, scalable SV-UVM testbenches and write test sequences.
• Verify PCIe subsystems and other interfaces at block and subsystem levels.
• Write assertions, checkers, and coverage; analyze gaps and drive closure.
• Build firmware-based simulations in C; mirror real FW behavior to validate HW/SW interactions.
• Reproduce silicon failures in simulation and perform deep debug to root cause.
• Automate flows with Python/Perl/Shell scripting.
• Collaborate with AEs/FW on debug, feature implementation, and spec contributions.

Skills

RTL verification

SV/UVM

PCIe verification

Gate-level simulation

Firmware-based simulation

RTL design

Computer architecture

Debugging

Collaboration

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Testbenches

Job description

Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You’ll develop verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.

The base salary range is 130,000 - 160,000 USD per year with discretionary bonus, equity, and a full range of medical and other benefits.