Senior Design Verification Engineer (IP/SoC)

Apple Inc.; United States; On-site; USD 180,000 - 250,000; Full time

Job summary

Apple Inc. is seeking an outstanding design verification engineer to enable first silicon for IP designs across the SoC. You will define DV methodology, develop verification environments, and write tests with checkers, aiming for bug-free silicon and robust coverage.

Responsibilities include creating test plans, building SystemVerilog/UVM stress infrastructure, debugging regressions, and leveraging LLMs to accelerate verification. A strong background in verification and scripting is required.

Qualifications

• BS degree in a technical subject with 10+ years of relevant industry experience.
• Deep knowledge of SystemVerilog and UVM.
• Experience with verification methodologies, tools, and test-benches.

Responsibilities

• Study design specification and create test plan.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Skills

SystemVerilog

UVM

OOP

LLMs for verification

Python

Education

BS degree in technical subject

Tools

Waveform viewers

Simulators

Formal verification tools

UPF power-aware verification

Job description

Apple Inc. is seeking an outstanding design verification engineer to enable first silicon for IP designs across the SoC. You will define DV methodology, develop verification environments, and write tests with checkers, aiming for bug-free silicon and robust coverage.

Responsibilities include creating test plans, building SystemVerilog/UVM stress infrastructure, debugging regressions, and leveraging LLMs to accelerate verification. A strong background in verification and scripting is required.