Design Verification Engineer

Socket.dev; Town of Texas (WI); On-site; USD 150,000 - 230,000; Full time

Job summary

Apple is seeking an outstanding Design Verification Engineer to enable first silicon for IP designs. You will own pre-silicon verification, establish DV methodology, and develop verification environments with stimulus, checkers, and coverage tracking.

You will drive test plans, debug failures, and report DV progress using a range of metrics, including use of LLMs to improve efficiency and quality. You will work on achieving bug-free silicon and will be responsible for scoping verification

Qualifications

• BS degree in a technical subject with 10+ years of relevant industry experience.
• Strong knowledge of OOP, SystemVerilog and UVM.

Responsibilities

• Establish DV methodology and test plans for pre-silicon verification.
• Develop verification environments with stimulus, checkers, and coverage metrics.
• Lead debugging, regression, and DV progress reporting using DV metrics.

Skills

OOP

SystemVerilog

UVM

Test-benches

Education

BS degree in technical subject area

Tools

Simulators

Waveform viewers

Automation scripts

Job description

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable. Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.

Minimum Qualifications

BS degree in technical subject area and a minimum 10 years relevant industry experience or equivalent.

Preferred Qualifications

Deep knowledge of OOP, SystemVerilog and UVMDeep knowledge in developing scalable and portable test-benchesStrong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulationsWorking experience using LLMs for efficiency and qualityExperience with power-aware (UPF) or similar verification methodologyExcellent knowledge of one of the scripting languages such as Python, Perl, TCLExperience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not requiredKnowledge of formal verification methodology is a plus but not requiredKnowledge of emulation for verification technologies is a plus but not required