Design Verification Engineer

Apple; Cary (NC); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple in Cary, NC seeks an outstanding design verification engineer to enable first silicon for IP designs and to craft verification environments across multiple IP blocks.

You will develop DV methodologies, write test plans, and build scalable test benches with stimulus, checkers, and coverage tracking, driving completion to RTL freeze and tape‑out. Experience with SystemVerilog/UVM and scripting is preferred.

Qualifications

• Minimum: bachelor’s degree in a technical field.
• BS degree with 3+ years of relevant industry experience preferred.

Responsibilities

• Establish DV methodology and test plan for IP designs.
• Develop verification environments with stimulus, checkers and assertions.
• Write tests, debug, measure coverage, and drive DV progress to sign‑off.
• Collaborate across teams for RTL freeze and tape‑out readiness.

Skills

SystemVerilog

UVM

Object‑Oriented Programming

Test bench development

Verification methodologies

LLMs for efficiency

Power-aware verification (UPF)

Scripting (Python, Perl, TCL)

PCIe/USB knowledge

DDR/other protocols

Formal verification knowledge

Emulation technologies

Education

Bachelor's degree

BS in technical field

Tools

Simulators

Waveform viewer

Build & run automation

Coverage tools

Liu/LLM tooling

Job description

Role Number: 200658373-1435

Summary

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.

This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.

Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.

Minimum Qualifications

• + Minimum requirement of a bachelors degree

Preferred Qualifications

• + BS degree in technical subject area and a minimum 3 years relevant industry experience strongly preferred
• + Strong knowledge of OOP, SystemVerilog and UVM
• + Strong knowledge in developing scalable and portable test-benches
• + Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
• + Some working experience using LLMs for efficiency and quality
• + Experience with power-aware (UPF) or similar verification methodology
• + Knowledge of one of the scripting languages such as Python, Perl, TCL
• + Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
• + Knowledge of formal verification methodology is a plus but not required
• + Knowledge of emulation for verification technologies is a plus but not required

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.