Design Verification Engineer - First Silicon SoC

Apple; Cary (NC); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple in Cary, NC seeks an outstanding design verification engineer to enable first silicon for IP designs and to craft verification environments across multiple IP blocks.

You will develop DV methodologies, write test plans, and build scalable test benches with stimulus, checkers, and coverage tracking, driving completion to RTL freeze and tape‑out. Experience with SystemVerilog/UVM and scripting is preferred.

Qualifications

• Minimum: bachelor’s degree in a technical field.
• BS degree with 3+ years of relevant industry experience preferred.

Responsibilities

• Establish DV methodology and test plan for IP designs.
• Develop verification environments with stimulus, checkers and assertions.
• Write tests, debug, measure coverage, and drive DV progress to sign‑off.
• Collaborate across teams for RTL freeze and tape‑out readiness.

Skills

SystemVerilog

UVM

Object‑Oriented Programming

Test bench development

Verification methodologies

LLMs for efficiency

Power-aware verification (UPF)

Scripting (Python, Perl, TCL)

PCIe/USB knowledge

DDR/other protocols

Formal verification knowledge

Emulation technologies

Education

Bachelor's degree

BS in technical field

Tools

Simulators

Waveform viewer

Build & run automation

Coverage tools

Liu/LLM tooling

Job description

Apple in Cary, NC seeks an outstanding design verification engineer to enable first silicon for IP designs and to craft verification environments across multiple IP blocks.

You will develop DV methodologies, write test plans, and build scalable test benches with stimulus, checkers, and coverage tracking, driving completion to RTL freeze and tape‑out. Experience with SystemVerilog/UVM and scripting is preferred.