Senior Design Verification Engineer - Coherent Interconnect

Bzpp; United States; Presencial; USD 151.000 - 252.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical insurance

Dental insurance

Vision insurance

401(k)

Onsite lunch

Tuition assistance

Paid time off

Descripción de la vacante

Samsung Austin Research and Development Center (SARC) seeks a seasoned Design Verification Engineer for coherent interconnect IPs powering Exynos SoCs. You will verify system IP, build scalable testbenches, and drive verification methodologies across block- and top-level environments.

Collaboration with global teams and adoption of advanced verification practices are essential. You will architect reusable environments, create stimulus, assertions, and coverages, and contribute to test plans,

Formación

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years with a Master’s Degree, or 6+ years with a Ph.D.
• 8+ years of professional experience in a design verification role building testbenches from scratch
• Strong background in design verification of coherent interconnects, combined experience with LPDDR memory controllers is a plus
• Proficiency in ARM protocols – CHI, AXI, ACElite, APB
• Strong coding skills in System Verilog, UVM
• Experience with Git version control, Unix/Perl scripting
• Formal verification skills will be a plus
• Strong communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.

Responsabilidades

• Verify System IP including coherent interconnects and caches.
• Architect, develop, and maintain reusable verification environments and testbenches.
• Contribute to test plans, reviews, debugging, and coverage analysis.
• Adopt power-aware verification with UPF and gate-level simulations.
• Collaborate with design, SoC, physical design, and performance verification teams.

Conocimientos

SystemVerilog

UVM

ARM CHI/AXI

Testbench design

Collaboration

Educación

Bachelor's in CS/Engineering

Master's in CS/Engineering

Ph.D. in CS/Engineering

Herramientas

Git

Unix/Perl

UPF

Descripción del empleo

Samsung Austin Research and Development Center (SARC) seeks a seasoned Design Verification Engineer for coherent interconnect IPs powering Exynos SoCs. You will verify system IP, build scalable testbenches, and drive verification methodologies across block- and top-level environments.

Collaboration with global teams and adoption of advanced verification practices are essential. You will architect reusable environments, create stimulus, assertions, and coverages, and contribute to test plans,