Senior Coherent Interconnect RTL Architect

Bzpp; United States; On-site; USD 151,000 - 252,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Life insurance

401(k)

Free onsite lunch

Employee purchase program

Tuition assistance

Paid time off

Student loan program

Wellness incentives

Job summary

Samsung Austin R&D Center (SARC) and ACL are seeking a senior RTL design engineer to drive coherent interconnect IP and LLC development. You will collaborate with architects, verification, and CAD teams to deliver high-performance designs and meet strict PPA goals.

Ideal candidates have extensive Verilog RTL experience, with strong understanding of ASIC flows and mentoring skills. This is an on-site U.S. role with a comprehensive total rewards program, including health benefits and 401(k).

Qualifications

• Experience owning RTL design for coherent interconnects or memory controllers.
• Strong background in high performance digital designs and RTL to gate flow.
• Knowledge of ASIC design flow including synthesis, prototyping, ECO and lab debug.
• Excellent communication and mentoring abilities.

Responsibilities

• Drive timely development of custom coherent interconnect IP/LLC blocks.
• Partner with architects to define next-gen coherent interconnects and LLC.
• Perform microarchitecture development from exploration to detailed specs.
• Verify functionality with the verification team and meet timing/area goals.
• Produce quality RTL on schedule meeting PPA targets.
• Mentor junior engineers and collaborate with CAD/physical design teams.

Skills

Verilog expertise

RTL design ownership

ASIC design flow knowledge

Team leadership/mentoring

Communication skills

Education

Bachelor's in Computer Science/Computer Engineering

Master's degree

PhD

Tools

AMBA5 CHI

AMBA4 ACE/AXI

DFT / timing analysis tools

Job description

Samsung Austin R&D Center (SARC) and ACL are seeking a senior RTL design engineer to drive coherent interconnect IP and LLC development. You will collaborate with architects, verification, and CAD teams to deliver high-performance designs and meet strict PPA goals.

Ideal candidates have extensive Verilog RTL experience, with strong understanding of ASIC flows and mentoring skills. This is an on-site U.S. role with a comprehensive total rewards program, including health benefits and 401(k).