[Samsung Electronics America] Micro-architect/Logic Designer, Coherent Interconnect 채용

Samsung Electronics America; United States; Vor Ort; USD 151.000 - 252.000; Vollzeit

Benefits dieser Stelle

Medical

Dental

Vision

Life insurance

401(k)

Free onsite lunch

Employee purchase program

Tuition assistance

Paid time off

Student loan program

Wellness incentives

Zusammenfassung

Samsung Austin R&D Center (SARC) and ACL are seeking a senior RTL design engineer to drive coherent interconnect IP and LLC development. You will collaborate with architects, verification, and CAD teams to deliver high-performance designs and meet strict PPA goals.

Ideal candidates have extensive Verilog RTL experience, with strong understanding of ASIC flows and mentoring skills. This is an on-site U.S. role with a comprehensive total rewards program, including health benefits and 401(k).

Qualifikationen

• Experience owning RTL design for coherent interconnects or memory controllers.
• Strong background in high performance digital designs and RTL to gate flow.
• Knowledge of ASIC design flow including synthesis, prototyping, ECO and lab debug.
• Excellent communication and mentoring abilities.

Aufgaben

• Drive timely development of custom coherent interconnect IP/LLC blocks.
• Partner with architects to define next-gen coherent interconnects and LLC.
• Perform microarchitecture development from exploration to detailed specs.
• Verify functionality with the verification team and meet timing/area goals.
• Produce quality RTL on schedule meeting PPA targets.
• Mentor junior engineers and collaborate with CAD/physical design teams.

Kenntnisse

Verilog expertise

RTL design ownership

ASIC design flow knowledge

Team leadership/mentoring

Communication skills

Ausbildung

Bachelor's in Computer Science/Computer Engineering

Master's degree

PhD

Tools

AMBA5 CHI

AMBA4 ACE/AXI

DFT / timing analysis tools

Jobbeschreibung

Position SummarySamsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us!

Role and Responsibilities

• Drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks.
• Partner with architects to help define next-generation Samsung coherent interconnects and LLC.
• Perform microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and arriving at a detailed specification.
• Work alongside the verification team to verify the functionality and correctness of the design.
• Collaborate with implementation to achieve your timing and area.
• Produce quality RTL on schedule meeting PPA goals.
• Engage with performance and power team on achieving performance and power goals.
• Work with the physical design and CAD team to resolve implementation level details.
• Help mentor junior engineers in the team.

Skills and Qualifications

• 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD.
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs.
• Demonstrated successful architectural through RTL design experience on high performance digital designs.
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols.
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Preferred candidates will possess the following:

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of coherent interconnect, memory controller, and/or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

Total Rewards

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,000 and $251,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

• medical
• dental
• vision
• life insurance
• 401(k)
• free onsite lunch
• employee purchase program
• tuition assistance (after 6 months)
• paid time off
• student loan program
• wellness incentives

In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Trade Secrets

By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.