Senior Verification Engineer - Coherent Mesh Interconnect

Arm Limited; Austin (TX); Hybrid; USD 198,100 - 268,000; Full time

Job summary

Arm Limited in Austin, Texas is seeking a Design Verification Engineer to join their team and contribute to critical AI developments. The ideal candidate should have 7+ years of verification/RTL design experience, and a solid foundation in CPU microarchitecture.

Responsibilities include building verification plans, developing SystemVerilog/UVM test benches, and collaborating with architects and designers. The position offers a salary range of $198,100-$268,000 per year and supports a hybrid working model.

Qualifications

• 7+ years of hands-on experience in verification/RTL design.
• Experience with cache coherence, memory systems, and bus protocols.
• Previous experience in System Verilog/UVM constrained-random testbenches.

Responsibilities

• Build and maintain detailed verification plans and strategies.
• Debug and develop new features alongside architects and designers.
• Architect and develop efficient SystemVerilog/UVM based test benches.

Skills

Hands-on experience in verification/RTL design

CPU microarchitecture knowledge

Experience in System Verilog/UVM

Education

Bachelors, Masters or PhD in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog

UVM

Python

Perl

Job description

Arm Limited in Austin, Texas is seeking a Design Verification Engineer to join their team and contribute to critical AI developments. The ideal candidate should have 7+ years of verification/RTL design experience, and a solid foundation in CPU microarchitecture.

Responsibilities include building verification plans, developing SystemVerilog/UVM test benches, and collaborating with architects and designers. The position offers a salary range of $198,100-$268,000 per year and supports a hybrid working model.