Senior Design Verification Engineer – CPU Subsystem

ALTEN; California (MO); On-site; USD 90,000 - 130,000; Full time

Job summary

ALTEN seeks an experienced verification engineer to verify CPU subsystems and SoC interfaces using SystemVerilog/UVM. The role involves developing verification plans, UVM testbenches, and coverage metrics, while ensuring signoff with Architecture and RTL teams.

The candidate will verify interconnects, interrupts, coherency, power management, and error handling, executing regressions and debug efforts to close coverage gaps.

Qualifications

• Strong SystemVerilog/UVM expertise.
• Experience verifying CPU subsystems or SoC integration.
• Good understanding of AXI/AHB/APB and standard SoC interfaces.
• Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
• Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).

Responsibilities

• Verify CPU subsystem and standard interfaces using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify CPU subsystem functionality, interconnects, interrupts, coherency, power management, and exception handling.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Skills

SystemVerilog/UVM

CPU/SoC verification

SoC interfaces AXI/AHB/APB

Assertions & coverage

VIP integration

Scripting (Python/Perl/Shell)

Tools

Xcelium

VCS

Questa

Job description

Experience: 5–12+ Years

Responsibilities

• Verify CPU subsystem and standard interfaces using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify CPU subsystem functionality, interconnects, interrupts, coherency, power management, and exception handling.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Required Skills

• Strong SystemVerilog/UVM expertise.
• Experience verifying CPU subsystems or SoC integration.
• Good understanding of AXI/AHB/APB and standard SoC interfaces.
• Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
• Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).