Senior Design Verification Engineer

ApTask; United States; On-site; USD 120,000 - 180,000; Full time

Job summary

ApTask is seeking a verification engineer to own planning and execution for complex ASIC/SoC blocks from test plan through sign-off, translating designs into measurable coverage goals.

You will apply constrained-random, formal methods, and directed testing, develop environments and scoreboards, and mentor junior engineers while driving coverage closure and sign-off readiness.

Qualifications

• Bachelor's degree in EE/CE or 7+ years equivalent experience.
• 5+ years in ASIC/SoC functional verification.
• Hands-on SystemVerilog, UVM or formal testbench development.
• Experience with metric-driven verification for planning and coverage.
• Experience verifying complex digital control and datapath logic.

Responsibilities

• Own verification planning and execution from test plan to sign-off.
• Translate designs into verification strategies and coverage goals.
• Select verification methods including constrained-random, formal, and directed testing.
• Develop verification environments, scoreboards, monitors, coverage, and assertions.
• Drive functional coverage closure, regression health, and sign-off readiness.
• Build verification infrastructure, regression and CI, and reuse strategies across levels.
• Apply AI-assisted verification for stimulus generation, regression triage, and coverage analytics.
• Review testbench architecture and mentor junior engineers in verification.

Skills

Constrained-random verification

Metric-driven verification

Digital control & datapath debugging

Mentoring junior engineers

Education

Bachelor's degree in Electrical Engineering or Computer Engineering or related field

Tools

SystemVerilog

UVM

Formal verification

Job description

• • Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
• • Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios.
• • Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing.
• • Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
• • Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.
• • Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels.
• • Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.
• • Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology.

Skills: Basic Qualifications:

• • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or 7+ years equivalent experience.
• • Minimum five years of professional experience in ASIC or SoC functional verification.
• • Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance.
• • Experience with metric-driven verification for planning, assertions, and functional coverage closure.
• • Experience verifying complex digital control and datapath logic, including RTL and system-level debug. Preferred Qualifications:
• • Background in space-based communications, wireless communications, or modem, baseband, or DSP hardware.
• • Experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis.
• • Formal verification experience on production silicon, including connectivity, register maps, arbitration, CDC, or security properties.
• • Experience with interconnect or NoC verification covering performance, bandwidth, QoS, and deadlock analysis.
• • Experience verifying fault tolerance and reliability features such as ECC, redundancy schemes, or fault injection.
• • Experience developing C-based or portable stimulus for SoC, CPU boot, and firmware-driven test scenarios.
• • Experience applying AI, ML, or LLM tooling to stimulus generation, regression triage, or coverage analysis.