Senior Design/SDC Engineer - Timing & STA Expert (Onsite)

Inabia-Software-; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Inabia-Software- seeks a diligent Design/SDC Engineer in San Jose, CA for an onsite contract role. The engineer will drive timing constraints across fullchip designs, collaborate with frontend/back-end teams, and guide SDC development for seamless physical design closure.

The position emphasizes strong STA skills and scripting for automation. The role involves mentoring RTL owners, creating clocking diagrams, and promoting block-to-fullchip SDC methodologies.

Qualifications

• 7+ years of ASIC or related experience.
• Experience with block/full chip SDC development in functional and test modes.
• Proficient in Static Timing Analysis with PrimeTime/Tempus.

Responsibilities

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation.

Skills

Analytical thinking

ASIC/SoC design

Timing constraints understanding

Collaboration

Scripting

Education

Bachelor’s Degree in Electrical or Computer Engineering

Master’s Degree in Electrical or Computer Engineering

Tools

PrimeTime/Tempus

Synopsys DC/DCG/FC

Conformal Constraint Designer (CCD)

Verilog/SystemVerilog

Job description

Inabia-Software- seeks a diligent Design/SDC Engineer in San Jose, CA for an onsite contract role. The engineer will drive timing constraints across fullchip designs, collaborate with frontend/back-end teams, and guide SDC development for seamless physical design closure.

The position emphasizes strong STA skills and scripting for automation. The role involves mentoring RTL owners, creating clocking diagrams, and promoting block-to-fullchip SDC methodologies.