Senior ASIC Design/SDC Engineer – Onsite in San Jose

Inabia-Software-

San Jose (CA)

On-site

USD 170,000 - 260,000

Full time

3 days ago

Be an early applicant

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

Arrow Electronics is seeking an experienced ASIC Design/SDC Engineer to join our team in San Jose, onsite from day one. You will oversee fullchip SDCs, drive timing closure across multiple modes, and work with front-end and back-end teams to refine constraints for seamless physical design closure.

You will apply PrimeTime/Tempus for static timing analysis, develop automation scripts, and mentor others in SDC development.

Qualifications

Bachelors Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience.
Masters Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience.
Experience with block/full chip SDC development in functional and test modes.
Experience in Static Timing Analysis and STA tools like PrimeTime/Tempus.
Understanding of clocking and async boundaries.
Experience with synthesis tools (Synopsys DC/DCG/FC) and Verilog/SystemVerilog.

Responsibilities

Oversee fullchip SDCs and close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block/top-level IP integration.
Develop methodology to promote block level SDCs to fullchip and bring fullchip changes back to block level.
Ensure correctness and quality of SDCs early in the design cycle.
Review block level SDCs and clocking diagrams and mentor RTL design owners on SDC development.
Create fullchip clocking diagrams and related documentation.