ASIC Design/SDC Engineer

Inabia Software & Consulting Inc.; San Jose (CA); Presencial; USD 140 000 - 190 000; Tempo integral

Resumo da oferta

Arrow Electronics in San Jose, CA is seeking an experienced ASIC Design/SDC Engineer to own fullchip SDCs and guide timing constraints for seamless physical design closure of next-generation networking chips.

You will collaborate with Front-end and Back-end teams, review block-level SDCs, and mentor RTL designers on SDC development, contributing to efficient methodologies and comprehensive documentation.

Qualificações

• Minimum 7+ years in ASIC/related field with Bachelor’s or 5+ years with Master’s.
• Experience with block/full-chip SDC development in functional and test modes.
• Experience in Static Timing Analysis with PrimeTime/Tempus.

Responsabilidades

• Oversee fullchip SDCs with design and DFT teams to close timing.
• Mentor RTL designers on SDC development.
• Develop methodologies to promote block-level SDCs to fullchip.
• Create fullchip clocking diagrams and documentation.

Conhecimentos

STA expertise

Full-chip SDC

Verilog/SystemVerilog

Python scripting

Clocking analysis

Digital design concepts

Team collaboration

Formação académica

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Ferramentas

PrimeTime

Tempus

Conformal CCD

DC/DCG/FC

Descrição da oferta de emprego

• Job Title : ASIC Design/SDC Engineer
• Client: Arrow Electronics
• Experience Required:8+ years (Relevant)
• Work Location: San Jose CA (Day-1 Onsite)
• Visa: All visa, except H1B transfer
• C2C engagements are allowed.

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking chips.

Responsibilities include:

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications

• Bachelors Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Masters Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
• Experience with block/full chip SDC development in functional and test modes.
• Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
• Understanding of related digital design concepts (eg. clocking and async boundaries)
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications

• Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
• Experience with Spyglass CDC and glitch analysis
• Experience using Formal Verification: Synopsys Formality and Cadence LEC.
• Experience with scripting languages such as Python, Perl, or TCL