Senior Design/SDC Engineer: Full-Chip Timing, San Jose

Inabia Software & Consulting Inc.; San Jose (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

Inabia Software & Consulting Inc. in San Jose, CA is seeking a Design/SDC Engineer to help close fullchip timing across multiple modes.

The role focuses on SDC development, STA analysis, and collaboration with front-end and back-end teams to refine timing constraints for seamless physical design closure. The candidate will leverage PrimeTime/Tempus and Synopsys tools, work with RTL design owners, and contribute to developing scalable methods for promoting block level SDCs to fullchip while

Qualifications

• Bachelor’s or Master’s degree in electrical/computer engineering with relevant ASIC experience.
• 7+ years (Bachelor) or 5+ years (Master) of ASIC or related work experience.
• Experience with block/full chip SDC development in functional and test modes.
• Familiarity with timing analysis and SDC/STA tools.

Responsibilities

• Oversee fullchip SDCs and coordinate with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to perform block level RTL design or block/top-level IP integration.
• Develop and apply methodology to promote block level SDCs to fullchip and feed changes back to block level.
• Develop and apply methodology to ensure correctness and quality of SDCs early in the design cycle.
• Review block level SDCs and clocking diagrams and mentor RTL design owners on SDC development.
• Create fullchip clocking diagrams and related documentation.

Skills

Analytical skills

Timing constraints understanding

Team collaboration

Automation scripting

Education

Bachelor’s Degree in Electrical or Computer Engineering

Master’s Degree in Electrical or Computer Engineering

Tools

PrimeTime/Tempus

Synopsys DC/DCG/FC

Verilog/SystemVerilog

Synthesis tools

Job description

Inabia Software & Consulting Inc. in San Jose, CA is seeking a Design/SDC Engineer to help close fullchip timing across multiple modes.

The role focuses on SDC development, STA analysis, and collaboration with front-end and back-end teams to refine timing constraints for seamless physical design closure. The candidate will leverage PrimeTime/Tempus and Synopsys tools, work with RTL design owners, and contribute to developing scalable methods for promoting block level SDCs to fullchip while