Senior Design Engineer - ASIC/FPGA (Remote, 6m Contract)

System One; El Segundo (CA); Remote; USD 179,000 - 183,000; Full time

Job summary

System One is seeking a Sr. Design Engineer for a 6-month contract to design digital ASICs and FPGAs, with relocation to Southern CA (El Segundo, CA) or Austin, TX. Remote work is allowed, with relocation requirements.

The role requires 7+ years in ASIC/FPGA design, HDL proficiency (VHDL/Verilog/SystemVerilog), and Linux development experience, plus verification and test bench development expertise.

Qualifications

• 7+ years of experience in ASIC design and implementation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Experience with FPGA & ASIC design.
• Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog).
• Experience with Linux development environment.
• Experience with design verification and test bench development.

Responsibilities

• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs.
• Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog).
• Develop verification methodologies and test benches for block and system-level verification.
• Create and execute test plans, develop test harnesses, and implement coverage models.
• Conduct timing analysis, noise analysis, and other signoff checks.
• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.
• Support lab integration and troubleshooting activities.
• Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.

Skills

ASIC design

FPGA design

HDL programming

Linux development

Test benches

Education

Bachelor's degree in Electrical Engineering or related

Tools

VHDL

Verilog

SystemVerilog

Job description

System One is seeking a Sr. Design Engineer for a 6-month contract to design digital ASICs and FPGAs, with relocation to Southern CA (El Segundo, CA) or Austin, TX. Remote work is allowed, with relocation requirements.

The role requires 7+ years in ASIC/FPGA design, HDL proficiency (VHDL/Verilog/SystemVerilog), and Linux development experience, plus verification and test bench development expertise.