Design Engineer Sr.

System One

El Segundo (CA)

A distancia

USD 179.000 - 183.000

Jornada completa

Hace 2 días
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Descripción de la vacante

System One is seeking a Sr. Design Engineer for a 6-month contract to design digital ASICs and FPGAs, with relocation to Southern CA (El Segundo, CA) or Austin, TX. Remote work is allowed, with relocation requirements.

The role requires 7+ years in ASIC/FPGA design, HDL proficiency (VHDL/Verilog/SystemVerilog), and Linux development experience, plus verification and test bench development expertise.

Formación

  • 7+ years of experience in ASIC design and implementation.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
  • Experience with FPGA & ASIC design.
  • Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog).
  • Experience with Linux development environment.
  • Experience with design verification and test bench development.

Responsabilidades

  • Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs.
  • Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog).
  • Develop verification methodologies and test benches for block and system-level verification.
  • Create and execute test plans, develop test harnesses, and implement coverage models.
  • Conduct timing analysis, noise analysis, and other signoff checks.
  • Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.
  • Support lab integration and troubleshooting activities.
  • Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.

Conocimientos

ASIC design
FPGA design
HDL programming
Linux development
Test benches

Educación

Bachelor's degree in Electrical Engineering or related

Herramientas

VHDL
Verilog
SystemVerilog

Descripción del empleo

Job Title: Design Engineer Sr.
Location: On-site or Remote: Remote - Must be willing to relocate to Southern CA (El Segundo, CA) OR Austin, TX
Type: 6-month contract with possibility of extension
Compensation: $130 - $133 per hour

Responsibilities
  • Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs
  • Implement designs using HDL (VHDL, Verilog, and/or System Verilog)
  • Develop verification methodologies and test benches for block and system-level verification
  • Create and execute test plans, develop test harnesses, and implement coverage models
  • Conduct timing analysis, noise analysis, and other signoff checks
  • Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
  • Support lab integration and troubleshooting activities
  • Resolve design issues and drive solutions for timing, congestion, and other implementation challenges

Requirements

Required: ANALYSIS DESIGN
  • 7+ years of experience in ASIC design and implementation
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
  • Experience with FPGA & ASIC design
  • Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
  • Experience with Linux development environment
  • Experience with design verification and test bench development

System One, and its subsidiaries including Mountain Ltd., are leaders in delivering outsourced services and workforce solutions across North America. We help clients get work done more efficiently and economically, without compromising quality. System One not only serves as a valued partner for our clients, but we offer eligible employees health and welfare benefits coverage options including medical, dental, vision, spending accounts, life insurance, voluntary plans, as well as participation in a 401(k) plan.

System One is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, age, national origin, disability, family care or medical leave status, genetic information, veteran status, marital status, or any other characteristic protected by applicable federal, state, or local law.

Ref: #404-IT Pittsburgh

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