Senior Defect Metrology Engineer — Substrate Packaging

Intel Corporation; Chandler (AZ); On-site; USD 104,000 - 199,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Paid vacation

Job summary

Intel Corporation in US (Arizona) is seeking a Defect Metrology Engineer to join the SPTD Yield team. You will help drive innovation in EMIB-T, glass core, EMIB scaling, and panel-level packaging for substrate and ATM factories serving Intel IPG and IFS customers.

Responsibilities include defect inspection, real-time data analysis, DOE summaries, and collaboration across teams. A strong background in semiconductor yield, defect metrology, and Python is required.

Qualifications

• Bachelor, Master, or PhD in Electrical Engineering, Chemical Engineering, Optical Engineering, Materials Science, Physics or related field with 1+ years to 3 years of semiconductor experience
• Experience in micro-contamination management within semiconductor manufacturing
• Experience as a Yield Analyst or Defect reduction owner or Defect metrology tool ownership
• Strong programming skills in Python

Responsibilities

• Use defect inspection tools to detect and resolve process issues and guide improvements with real-time data analysis
• Maintain flexibility to support evolving Yield space challenges
• Lead next-generation tool installation and qualification activities with diverse stakeholders
• Demonstrate independent leadership in defect metrology and yield enhancement initiatives
• Collaborate with factory teams to maintain WIP velocity and set up data flows for new tools
• Develop equipment roadmaps and work with suppliers to enhance tool capabilities
• Present tool capabilities and progress to leadership with a focus on defect metrology and micros-contamination expertise
• Perform descriptive statistical analysis and create visualizations and dashboards to aid decision-making
• Organize and interpret data insights and detect data anomalies

Skills

Python

Education

Bachelor of Science in Electrical Engineering

Master of Science in Electrical Engineering

PhD in Electrical Engineering

Job description

Intel Corporation in US (Arizona) is seeking a Defect Metrology Engineer to join the SPTD Yield team. You will help drive innovation in EMIB-T, glass core, EMIB scaling, and panel-level packaging for substrate and ATM factories serving Intel IPG and IFS customers.

Responsibilities include defect inspection, real-time data analysis, DOE summaries, and collaboration across teams. A strong background in semiconductor yield, defect metrology, and Python is required.