Senior DDR Validation Engineer & Debug Expert

Cadence Design Systems; San Francisco (CA); On-site; USD 115,000 - 213,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence Design Systems in California is seeking a experienced engineer to lead electrical and functional validation for next-generation DDR interfaces. You will design testing strategies, transform raw data into actionable insights, and drive cross-team debugging and reporting using Python.

The role requires strong background in DDR5/LPDDR5/LPDDR6/HBM4/GDDR7, collaboration across engineering and customer support, and delivering high-impact characterization that informs product decisions.

Qualifications

• M. Tech with 4+ years of experience or B. Tech with 6+ years.
• Experience validating DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7).
• Ability to transform raw data into actionable insights and reports.

Responsibilities

• Lead electrical and functional validation for next-generation DDR interfaces.
• Design testing strategies to accelerate post-silicon bring-up.
• Automate validation and reporting with Python.
• Drive cross-team debugging and deliver high-impact characterization reports.
• Provide world-class technical support for DDR IP challenges.

Skills

Electrical validation

DDR interfaces

Data analysis

Python scripting

Tools

JIRA

Job description

Cadence Design Systems in California is seeking a experienced engineer to lead electrical and functional validation for next-generation DDR interfaces. You will design testing strategies, transform raw data into actionable insights, and drive cross-team debugging and reporting using Python.

The role requires strong background in DDR5/LPDDR5/LPDDR6/HBM4/GDDR7, collaboration across engineering and customer support, and delivering high-impact characterization that informs product decisions.