Lead Design Engineer

Cadence Design Systems; San Francisco (CA); On-site; USD 115,000 - 213,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence Design Systems in California is seeking a experienced engineer to lead electrical and functional validation for next-generation DDR interfaces. You will design testing strategies, transform raw data into actionable insights, and drive cross-team debugging and reporting using Python.

The role requires strong background in DDR5/LPDDR5/LPDDR6/HBM4/GDDR7, collaboration across engineering and customer support, and delivering high-impact characterization that informs product decisions.

Qualifications

• M. Tech with 4+ years of experience or B. Tech with 6+ years.
• Experience validating DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7).
• Ability to transform raw data into actionable insights and reports.

Responsibilities

• Lead electrical and functional validation for next-generation DDR interfaces.
• Design testing strategies to accelerate post-silicon bring-up.
• Automate validation and reporting with Python.
• Drive cross-team debugging and deliver high-impact characterization reports.
• Provide world-class technical support for DDR IP challenges.

Skills

Electrical validation

DDR interfaces

Data analysis

Python scripting

Tools

JIRA

Job description

Aug 19, 2026

$114,800 - $213,200/year

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description:

• Lead cutting-edge electrical and functional validation for next-generation DDR interfaces such as DDR5, LPDDR5, LPDDR6, HBM4 and GDDR7.
• Design and execute innovative testing strategies to accelerate post-silicon bring-up.
• Transform raw data into actionable insights through advanced analysis and visualization.
• Resolve complex issues by driving JIRA-based debug workflows and collaborating across teams.
• Deliver high-impact characterization reports that influence product decisions and customer success.
• Automate using Python for validation, data processing, and reporting.
• Be the go-to expert for customer DDR IP challenges, ensuring rapid debug and world-class technical support.

Experience:

M. Tech + 4 years' experience or B. Tech with 6 years' experience.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

Cadence is a leader in electronics and system design, offering innovative software, hardware, and IP solutions for diverse industries, including automotive, aerospace, and healthcare.

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2655 Seely Avenue, San Jose, California 95134, US