Lead Design Engineer - DDR Validation & Insight Automation

Cadence; San Jose (CA); On-site; USD 114,800 - 213,200; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Paid vacation and holidays

Job summary

Cadence in San Jose, California is seeking a skilled individual to lead electrical and functional validation for advanced DDR interfaces such as DDR5 and HBM4. The ideal candidate will create innovative testing strategies, transform data into insights, and drive collaborative debug processes.

The role requires M. Tech + 4 years or B. Tech with 6 years of experience. The position offers a salary range of $114,800 to $213,200, along with benefits including paid vacation, 401(k), and a variety of medical plans.

Qualifications

• Proficiency in electrical and functional validation for DDR interfaces.
• Strong experience in developing innovative testing strategies and post-silicon bring-up.
• Ability to automate processes using Python for validation and reporting.

Responsibilities

• Lead validation for next-generation DDR interfaces like DDR5 and HBM4.
• Transform raw data into insights through advanced analysis.
• Drive JIRA-based debug workflows and collaborate across teams.

Skills

Electrical validation

Functional validation

Testing strategies

Data analysis

Python automation

Education

M. Tech + 4 years’ experience or B. Tech with 6 years’ experience

Tools

JIRA

Job description

Cadence in San Jose, California is seeking a skilled individual to lead electrical and functional validation for advanced DDR interfaces such as DDR5 and HBM4. The ideal candidate will create innovative testing strategies, transform data into insights, and drive collaborative debug processes.

The role requires M. Tech + 4 years or B. Tech with 6 years of experience. The position offers a salary range of $114,800 to $213,200, along with benefits including paid vacation, 401(k), and a variety of medical plans.