Lead MTS Applications Engineer – DDR5 & I2C Validation

Rambus; San Jose (CA); Hybrid; USD 117,000 - 168,000; Full time

Benefits offered by this job

Bonus

Equity

401(k) matching

Stock purchase plan

Medical and dental benefits

Time off

Job summary

Rambus, a premier chip and silicon IP provider, is seeking a Lead MTS Application Engineer to join the Memory Interface team in San Jose, CA. This full-time role reports to the Director of Application and Validation and focuses on validation across bench and system for DDR5 enablement devices.

The candidate will validate digital ASIC bench tests, develop Python scripts for bench automation, and provide post-silicon support while collaborating with design, operation, and development teams.

Qualifications

• 5+ years of post-silicon digital ASIC bench validation.
• B.S. or M.S. in Electrical or Computer Engineering or Computer Engineering.
• Experience with lab automation in Python.
• Experience with I2C/I3C protocols.
• New graduates with digital design/validation background are welcome.

Responsibilities

• Bench characterization and validation of I2C/I3C protocols.
• Developing Python scripts for bench automation.
• Support customers in understanding and resolving their issues.
• Provide post-silicon bring-up support, interface with design, operation, and development.

Skills

Python scripting

I2C/I3C protocols

Post-silicon validation

Bench characterization

Education

B.S. or M.S. in Electrical or Computer Engineering

Job description

Rambus, a premier chip and silicon IP provider, is seeking a Lead MTS Application Engineer to join the Memory Interface team in San Jose, CA. This full-time role reports to the Director of Application and Validation and focuses on validation across bench and system for DDR5 enablement devices.

The candidate will validate digital ASIC bench tests, develop Python scripts for bench automation, and provide post-silicon support while collaborating with design, operation, and development teams.