DDR Memory Interface System Validation Lead Engineer

191 Altera Corporation; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

191 Altera Corporation is looking for a highly motivated DDR5 / LPDDR5 Memory Validation Engineer in San Jose, California. This role involves driving validation and characterization activities for advanced memory interfaces on next-generation FPGA devices.

The ideal candidate should possess a Bachelor's or Master's degree in Electrical Engineering and have over 8 years of experience in memory subsystem validation. The position offers a competitive salary range between $149,100 and $215,000.

Qualifications

• 8+ years of industry experience in memory subsystem validation.
• Experience with silicon validation or high-speed interface validation.

Responsibilities

• Own DDR5 and LPDDR5 memory subsystem validation.
• Create comprehensive validation environments for memory interfaces.
• Perform functional and electrical validation of memory controllers.

Skills

Memory subsystem validation

Silicon validation

High-speed interface validation

Debugging complex issues

Use of oscilloscopes and logic analyzers

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Protocol analyzers

Traffic generators

Job description

Altera is the world’s largest pure‑play FPGA solutions provider, offering programmable technologies that help customers differentiate, innovate, and scale across AI, cloud, networking, and edge markets.

About the Role

We are seeking a highly motivated and experienced DDR5 / LPDDR5 Memory Validation Engineer to join our Silicon and Platform Validation organization. In this role, you will drive validation, characterization, and debug activities for advanced DDR5 and LPDDR5 memory interfaces on next‑generation FPGA devices. You will work closely with architecture, silicon design, board design, firmware, signal integrity, and software teams to ensure industry‑leading quality, reliability, performance, and interoperability across memory subsystems and high‑speed I/O platforms. This position offers the opportunity to work hands‑on with cutting‑edge memory technologies, advanced PHY architectures, and high‑speed validation infrastructure while influencing future FPGA platform capabilities and validation methodologies.

Key Responsibilities

• Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs.
• Create, define, and develop comprehensive system‑level validation environments and test suites for advanced memory interface validation.
• Perform pre‑silicon and post‑silicon functional and electrical validation of DDR5 and LPDDR5 controllers, PHYs, and associated high‑speed interfaces.
• Develop and execute validation plans covering memory initialization and training, read/write functional validation, system margining and stress testing, frequency scaling, memory controller features, stability and reliability validation, error injection and recovery testing, timing characterization, compliance checks, interoperability testing, and performance validation according to JEDEC specifications.
• Analyze signal integrity and timing behavior for high‑speed memory interfaces, including eye diagrams, jitter, and timing margins.
• Debug complex silicon, firmware, board‑level, and system‑level issues involving memory subsystems and PHY behavior.
• Collaborate with hardware board design teams on high‑speed memory channel implementation, including stack‑up reviews, routing strategies, SI/PI considerations, memory topology optimization, termination and power delivery schemes, and review of schematics, layouts, and board design guidelines for DDR5 and LPDDR5 implementations.
• Utilize industry‑standard protocol analyzers, oscilloscopes, logic analyzers, and traffic generators for debug and characterization.
• Develop, standardize, and maintain validation methodologies, automation frameworks, and measurement flows to improve validation scalability and efficiency.
• Partner with silicon design, package, board, firmware, and software teams to drive root‑cause analysis and issue resolution.
• Collaborate with pre‑silicon validation teams to improve post‑silicon coverage and future debug capabilities.
• Drive innovation in validation infrastructure, automation, and platform enablement to improve throughput and test coverage.

Salary Range

$149,100 – $215,000 USD (Bay Area, California)

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.
• Minimum of 8+ years of industry experience in memory subsystem validation, silicon validation, or high‑speed interface validation.

Employment Information

• Job type: Regular
• Shift: Shift1 (United States of America)
• Primary location: San Jose, California, United States

Equal Employment Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.