Senior DDR5/LPDDR5 Memory Validation Lead

Altera; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

Altera in San Jose is seeking a highly skilled DDR5 / LPDDR5 Memory Validation Engineer to lead validation and debug activities for advanced memory interfaces on cutting-edge FPGA devices.

The role requires significant industry experience in memory subsystem validation and strong collaboration skills across multiple teams. The salary range is $149,100 - $215,000 USD, with additional incentive opportunities.

Qualifications

• Minimum of 8+ years of industry experience in memory subsystem validation or high-speed interface validation.
• Experience with DDR5 and LPDDR5 memory technologies.
• Ability to collaborate with cross-functional teams across architecture, silicon design, and firmware.

Responsibilities

• Own DDR5 and LPDDR5 memory subsystem validation.
• Create and execute validation plans and strategies.
• Analyze timing behavior and perform compliance checks.
• Debug issues involving memory subsystems and collaborate on design implementation.

Skills

Memory subsystem validation

High-speed interface validation

Debugging

Signal integrity analysis

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

Protocol analyzers

Oscilloscopes

Logic analyzers

Job description

Altera in San Jose is seeking a highly skilled DDR5 / LPDDR5 Memory Validation Engineer to lead validation and debug activities for advanced memory interfaces on cutting-edge FPGA devices.

The role requires significant industry experience in memory subsystem validation and strong collaboration skills across multiple teams. The salary range is $149,100 - $215,000 USD, with additional incentive opportunities.