Senior CPU Verification Engineer: SoC & Power Specialist

RiseMe; Austin (TX); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Hybrid work model

Competitive pay

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel is seeking a Senior CPU Design Verification Engineer to join the All Cores Engineering (ACE) group. You will lead pre-silicon verification of complex CPU/SoC logic for Atom cores, delivering robust designs before first silicon.

This hands-on role requires deep SystemVerilog/UVM expertise, strong debugging skills, and collaboration with CPU architects, RTL designers, and power teams to drive verification excellence and early risk mitigation.

Qualifications

• Bachelor’s or Master’s degree with relevant verification experience.
• Experience with SystemVerilog, UVM, and EDA tools.
• Pre-silicon verification of CPU/SoC designs.
• Debugging with SystemVerilog, C/C++, Linux simulations.
• Python or Perl scripting for automation.
• Exposure to RTL development and CPU microarchitecture.
• Understanding of power/thermal/perf verification flows.

Responsibilities

• Lead pre-silicon functional verification of CPU/SoC logic.
• Develop testbenches and UVM environments.
• Define and run system-level simulations to find issues.
• Debug RTL/microarchitecture and drive fixes.
• Collaborate with architects, RTL designers, and physical design teams.
• Maintain verification infrastructure and automation.
• Document verification strategies and participate in design reviews.

Skills

SystemVerilog

UVM

CPU/SoC verification

Debugging SystemVerilog

C/C++

Python

Linux

RTL development

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in related field

Tools

Simulation environments

EDA tools

RTL debugging tools

Job description

Intel is seeking a Senior CPU Design Verification Engineer to join the All Cores Engineering (ACE) group. You will lead pre-silicon verification of complex CPU/SoC logic for Atom cores, delivering robust designs before first silicon.

This hands-on role requires deep SystemVerilog/UVM expertise, strong debugging skills, and collaboration with CPU architects, RTL designers, and power teams to drive verification excellence and early risk mitigation.