Lead CPU Verification Architect — Equity Eligible

Cadence Design Systems; San Jose (CA); On-site; USD 186,000 - 345,000; Full time

Benefits offered by this job

Paid vacation

401(k) with match

Employee stock purchase plan

Medical/dental/vision plans

And more

Job summary

Cadence Design Systems seeks a Director of Design Verification to lead the Processor Verification team, overseeing verification of microprocessor cores and peripherals in a high-impact setting. The role requires deep DV expertise and strong leadership to guide 7–10 engineers.

Location includes San Jose, CA and Austin, TX, with a competitive salary and incentives. The ideal candidate will have 17+ years of verification experience, a BS in EE/CE, and mastery of SystemVerilog/UVM, assembly

Qualifications

• 17+ years of design verification experience.
• BS in EE/Computer Engineering.
• Proven experience leading/managing a team.
• Strong managerial and interpersonal skills.
• Excellent knowledge of computer architecture and design verification fundamentals.
• Thorough understanding of SystemVerilog, UVM, and other languages to build testbenches.
• Exposure to Perl or Unix shell scripting.
• Experience with assembly language programming.
• Experience with Gate Level Simulations and processor verification.

Responsibilities

• Lead and run the Processor Verification team for microprocessor cores.
• Craft verification plans and execute them to verify complex CPU designs.
• Implement simulation or emulation testbenches and diagnostics.
• Oversee coverage collection and closure.
• Collaborate with DV/Arch/Design/FW teams to define coverage scope.
• Track and report the work of 7-10 engineers.

Skills

Design verification

Leadership

Interpersonal skills

SystemVerilog/UVM

Scripting (Perl/Unix)

Assembly language

Gate level simulations

Education

BS in EE/Computer Engineering

Tools

SystemVerilog

UVM

Perl

Unix shell

Formal Verification

Job description

Cadence Design Systems seeks a Director of Design Verification to lead the Processor Verification team, overseeing verification of microprocessor cores and peripherals in a high-impact setting. The role requires deep DV expertise and strong leadership to guide 7–10 engineers.

Location includes San Jose, CA and Austin, TX, with a competitive salary and incentives. The ideal candidate will have 17+ years of verification experience, a BS in EE/CE, and mastery of SystemVerilog/UVM, assembly