Senior CPU Emulation Engineer — FPGA/RTL, Equity Eligible

Google; Town of Montana (WI); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking an experienced CPU Emulation Engineer, Silicon to push the boundaries of custom silicon solutions powering Google’s hardware products. You will help craft RTL partitions and FPGA-based validation, driving pre-silicon verification and performance benchmarking across enterprise emulation platforms.

Qualified candidates have a strong background in RTL design, emulation platforms, and automation scripting, with a track record of mentoring and delivering scalable hardware solutions

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8 years of experience with emulation or FPGA prototyping platforms.
• Experience in RTL design using Verilog or SystemVerilog.
• Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.

Responsibilities

• Architect and drive RTL partitioning, FPGA synthesis, and validation strategies for emulation platforms.
• Define and execute test suites, performance benchmarks, and software workloads for pre-silicon verification and system-level validation.
• Guide advanced debugging methodologies to isolate and resolve complex functional failures in multi-million gate subsystem designs.
• Lead initiatives to optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization across emulation farms.
• Architect custom automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline CI.

Skills

RTL design with Verilog/SystemVerilog

Automation scripting

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Synopsys ZeBu/HAPS

Cadence Palladium/Protium

Siemens Veloce

Job description

Google is seeking an experienced CPU Emulation Engineer, Silicon to push the boundaries of custom silicon solutions powering Google’s hardware products. You will help craft RTL partitions and FPGA-based validation, driving pre-silicon verification and performance benchmarking across enterprise emulation platforms.

Qualified candidates have a strong background in RTL design, emulation platforms, and automation scripting, with a track record of mentoring and delivering scalable hardware solutions