Senior CPU/RTL Design Verification Engineer

Anysilicon; Cupertino (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Cupertino, CA seeks talented verification engineers to ensure design functionality through comprehensive testing and verification.

You will collaborate with architecture and RTL designers to create robust test plans, develop complex tests in C and assembly, and extend UVM-based testbenches. The role requires strong C++/Verilog skills, experience with Verdi, and the ability to analyze coverage to ensure all test cases are exercised.

Qualifications

• Bachelor’s degree or foreign equivalent in Electrical Engineering, Computer Science, Electronics Engineering, or a related field.
• Experience in digital logic design, computer architecture, and CPU microarchitecture verification.
• Proficiency in C++ and Verilog for testbench and test plan development.
• Experience with assertion-based verification techniques using Verilog.
• Ability to debug functional issues in RTL using Verdi waveforms and provide root cause analysis.
• Experience in developing random generators for stimulus to verify CPU microarchitecture features.
• Skills in hardware debugging and validation to resolve complex component issues.
• Understanding of complex control logic structures for functionality verification.

Responsibilities

• Work closely with architecture and RTL designers to verify design functionality correctness.
• Develop and lead test plans and test environments.
• Create complex tests in assembly, C, or vectors based on test plans.
• Develop coverage monitors and analyze coverage to ensure all test cases are covered.
• Create checkers or C-based transactors for design verification.
• Extend and maintain SystemVerilog/UVM testbenches.
• Monitor large-scale gate-level or RTL regressions.
• Inspect waveforms using Verdi or other hardware debugging tools.
• Write Python/Perl utilities to scrub and aggregate regression data.
• Author and review detailed verification plans and coverage dashboards.
• Collaborate with cross-functional partners including architecture, validation, and firmware teams.

Skills

C++

Verilog

SystemVerilog

RTL verification

Education

Bachelor’s degree in Electrical Engineering or Computer Science

Tools

Verdi

UVM

Python

Job description

Apple Inc. in Cupertino, CA seeks talented verification engineers to ensure design functionality through comprehensive testing and verification.

You will collaborate with architecture and RTL designers to create robust test plans, develop complex tests in C and assembly, and extend UVM-based testbenches. The role requires strong C++/Verilog skills, experience with Verdi, and the ability to analyze coverage to ensure all test cases are exercised.