Senior CPU RTL Design Engineer - Architecture & Power

Intel; Phoenix (AZ); Hybrid; USD 141,910 - 269,100; Full time

Job summary

Intel is seeking a CPU Logic Design Engineer to drive RTL coding, verification and optimization for next‑gen CPU blocks, with emphasis on architecture and microarchitecture features. You will develop RTL and simulation for power, performance, area, and timing goals, ensuring design integrity for physical implementation.

Collaborate with SoC customers to enable seamless integration and high‑quality CPU performance, applying cross‑clock domain techniques, low‑power design methods, and scripting

Qualifications

• 7+ years RTL design experience with Verilog, V2K, or System Verilog.
• 5+ years energy-efficient and low-power design experience.
• 5+ years cross-clock domain crossing and power-aware design.
• 3+ years scripting with TCL, Perl, or Python.

Responsibilities

• Develop RTL coding, simulation for the CPU, and optimize logic.
• Define architecture and microarchitecture features of the CPU.
• Write RTL to meet power, performance, area, and timing goals.
• Ensure design integrity for physical implementation.
• Review verification plans and resolve failing RTL tests.
• Document MAS for CPU features.
• Collaborate with SoC customers for integration and performance.

Skills

RTL design

Verilog

SystemVerilog

V2K

Power-aware design

Cross-clock domain crossings

Python

TCL

Perl

Education

Bachelor's degree in electrical/computer engineering or computer science

Master's or PhD with 2+ years experience

Tools

UPF

Lint checks

Timing analysis tools

Job description

Intel is seeking a CPU Logic Design Engineer to drive RTL coding, verification and optimization for next‑gen CPU blocks, with emphasis on architecture and microarchitecture features. You will develop RTL and simulation for power, performance, area, and timing goals, ensuring design integrity for physical implementation.

Collaborate with SoC customers to enable seamless integration and high‑quality CPU performance, applying cross‑clock domain techniques, low‑power design methods, and scripting