CPU Core Logic Designer — RTL & SoC Integration

Intel; Folsom (CA); Hybrid; USD 122,440 - 172,860; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel is seeking an Experienced Hire for a CPU RTL design role in Folsom, California. The engineer will develop logic design, RTL coding, and simulation to support generation of cell libraries, functional units, and CPU IP blocks for full chip integration.

The position involves architecture/microarchitecture feature definition, RTL optimization for power, performance, and area, and verification plan reviews. Collaboration with SoC customers is essential.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or Computer Science with 2+ years experience, or Master's with 1+ years.
• 6+ months combined experience in System Verilog/Verilog/VHDL and/or VCS or similar simulator.
• Computer architecture and microarchitecture.
• Software/programming languages (i.e. C, C++, C#, Visual Basic/.NET, Perl, Python, Java, etc.).
• Modern energy efficient/low power logic design techniques, including those specifically applicable to high frequency optimization.

Responsibilities

• Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.
• Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Documents micro architectural specs (MAS) of the CPU features being designed.
• Supports SoC customers to ensure high quality integration of the CPU block.

Skills

RTL design

HDL languages

Computer architecture

Programming languages

Low power design

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master's degree in Electrical/Computer Engineering or Computer Science

Tools

VCS or similar simulator

Job description

Intel is seeking an Experienced Hire for a CPU RTL design role in Folsom, California. The engineer will develop logic design, RTL coding, and simulation to support generation of cell libraries, functional units, and CPU IP blocks for full chip integration.

The position involves architecture/microarchitecture feature definition, RTL optimization for power, performance, and area, and verification plan reviews. Collaboration with SoC customers is essential.