Senior CPU RTL Front-End Architect — AI-Driven Efficiency

Intel Corporation; Phoenix (AZ); On-site; USD 164,000 - 312,000; Full time

Job summary

Intel is seeking a Sr. CPU RTL Methodology Engineer to lead and execute RTL development strategies for high-performance silicon. You will drive front-end and cross-team collaboration to ensure power, performance, area, and timing targets are met across multiple domains.

The role emphasizes leadership in AI-assisted methodologies, architectural input, and a strong track record in CPU logic development, including x86 memory management execution.

Qualifications

• Minimum 6+ years of experience in silicon development of CPU logic.
• 5+ years of experience in technical leadership and in delivering successful IP Projects.
• Experience on x86 CPU microarchitecture and memory management execution.
• Experience driving front end methodologies and championing AI tools.

Responsibilities

• Demonstrated leadership and hands-on experience in leveraging AI tools and methodologies to drive efficiency gains in RTL coding and silicon development.
• Advances front-end methodologies and contributes to architectural discussions to enhance scalability.
• Develops strategies, tools, and techniques for RTL development and logic optimization to meet power, performance, area, and timing targets.
• Understands front-end and back-end flows with a track record across multiple domains.
• Collaborates with architecture, backend, and design teams to deliver industry-leading products.
• Builds and sustains a high-performing organization by upholding core values and behaviors.

Skills

CPU silicon

Technical leadership

x86 microarchitecture

Memory management

Front-end methodologies

AI tools

Education

Bachelor's degree in CS/EE

Master's degree

PhD

Job description

Intel is seeking a Sr. CPU RTL Methodology Engineer to lead and execute RTL development strategies for high-performance silicon. You will drive front-end and cross-team collaboration to ensure power, performance, area, and timing targets are met across multiple domains.

The role emphasizes leadership in AI-assisted methodologies, architectural input, and a strong track record in CPU logic development, including x86 memory management execution.