Senior CPU Microarchitecture & RTL Engineer

Qualcomm; Santa Clara (CA); On-site; USD 212,000 - 318,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a CPU RTL Design Engineer in Santa Clara, CA to work with chip architects on micro-architecture concepts and early product-life cycle involvement.

You will contribute to high-performance, low-power devices by developing microarchitecture, conducting architectural exploration, and owning RTL from specification through delivery. Experience with Verilog/VHDL and CPU optimization is required.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of Hardware/Software/Systems experience.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 7+ years of Hardware/Software/Systems experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6+ years of Hardware/Software/Systems experience.

Responsibilities

• Performance exploration with CPU modeling team.
• Microarchitecture development and detailed specification.
• RTL ownership with design, verification, and timing goals.
• Functional verification support for verification strategy execution.
• Performance verification to ensure RTL meets performance targets.
• Collaborate with multi-functional teams for design delivery including timing, area, and reliability.

Skills

CPU architecture

Verilog/VHDL

Waveform debugging

Perl/Python scripting

Performance optimization

Education

Bachelor's in EE/CE/CS

Master's in EE/CE/CS

PhD in EE/CE/CS

Tools

Simulators

Job description

Qualcomm Technologies, Inc. is seeking a CPU RTL Design Engineer in Santa Clara, CA to work with chip architects on micro-architecture concepts and early product-life cycle involvement.

You will contribute to high-performance, low-power devices by developing microarchitecture, conducting architectural exploration, and owning RTL from specification through delivery. Experience with Verilog/VHDL and CPU optimization is required.