CPU RTL Design Engineer

Intel; Phoenix (AZ); Hybrid; USD 141,910 - 269,100; Full time

Job summary

Intel is seeking a CPU Logic Design Engineer to drive RTL coding, verification and optimization for next‑gen CPU blocks, with emphasis on architecture and microarchitecture features. You will develop RTL and simulation for power, performance, area, and timing goals, ensuring design integrity for physical implementation.

Collaborate with SoC customers to enable seamless integration and high‑quality CPU performance, applying cross‑clock domain techniques, low‑power design methods, and scripting

Qualifications

• 7+ years RTL design experience with Verilog, V2K, or System Verilog.
• 5+ years energy-efficient and low-power design experience.
• 5+ years cross-clock domain crossing and power-aware design.
• 3+ years scripting with TCL, Perl, or Python.

Responsibilities

• Develop RTL coding, simulation for the CPU, and optimize logic.
• Define architecture and microarchitecture features of the CPU.
• Write RTL to meet power, performance, area, and timing goals.
• Ensure design integrity for physical implementation.
• Review verification plans and resolve failing RTL tests.
• Document MAS for CPU features.
• Collaborate with SoC customers for integration and performance.

Skills

RTL design

Verilog

SystemVerilog

V2K

Power-aware design

Cross-clock domain crossings

Python

TCL

Perl

Education

Bachelor's degree in electrical/computer engineering or computer science

Master's or PhD with 2+ years experience

Tools

UPF

Lint checks

Timing analysis tools

Job description

Job Details

Intel puts Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. If you have a big idea, let us do something wonderful together. Join us because at Intel we are building a better tomorrow.

Role and Impact

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting‑edge processors. You will drive the development of register transfer level (RTL) code and simulation for the CPU, enabling creation of cell libraries, functional units, and CPU IP blocks for integration into full‑chip designs. Your expertise will be pivotal in defining architecture and microarchitecture features, ensuring Intel continues to deliver innovative solutions that lead the industry in performance, energy efficiency, and design integrity. By contributing to the development and optimization of logic structures, you will help create technology that enriches the lives of every person on Earth while enabling Intel to achieve its broader mission of engineering a brighter future.

Key Responsibilities

• Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU.
• Participate in defining the architecture and microarchitecture features of the CPU design.
• Write RTL and optimize logic for power, performance, area, and timing goals.
• Ensure design integrity for physical implementation through effective strategies, tools, and methods.
• Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
• Document microarchitectural specifications (MAS) for the CPU features.
• Collaborate with SoC customers to ensure seamless integration and high‑quality performance of the CPU block.

Qualifications

Minimum Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or computer science with 7+ years of relevant experience; OR Master's degree with 5+ years of experience; OR PhD with 2+ years of experience.
• 7+ years experience in RTL design using Verilog, V2K, or System Verilog, with strong knowledge of hardware modeling and logic debug environments.
• 5+ years experience with modern energy‑efficient and low‑power logic design methods, including techniques applicable to high‑frequency optimization.
• 5+ years experience in cross‑clock domain crossings and power aware design.
• 3+ years experience in scripting languages such as TCL, Perl, or Python.

Preferred Qualifications

• Knowledge on CPU power‑management namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states and reset sequence handling.
• Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
• Experience with high‑speed circuit design and optimization, specifically for datapath, circuits, and arrays.
• Familiarity with circuit planning and timing convergence processes.
• Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
• Proficient with static timing analysis, UPF and lint checks.
• Good communication skills.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

Job Type

Experienced Hire

Location

Primary location: US, Texas, Austin. Additional locations: US, Arizona, Phoenix.

Work Model

This role will be eligible for a hybrid work model, allowing employees to split their time between working on‑site at their assigned Intel site and off‑site.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Salary Range

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - $269,100.00 USD.