Physical Design Engineer, 3D Technology

Google LLC; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google LLC in Sunnyvale, CA is seeking a Share Physical Design Engineer, 3D Technology to shape AI/ML hardware acceleration and TPU architecture within high-performance computing environments.

You will collaborate across technology, physical design, circuit design, and hardware architecture teams, driving 3D technology flows from inception to tapeout and optimizing across PPA for cutting-edge Google TPU platforms.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4 years of experience with physical design and 3D integration technologies (3D-IC, 2.5D, TSV, etc.).
• Experience using industry-standard design tools (Synopsys, Cadence, Siemens EDA/Mentor).

Responsibilities

• Drive development of a leading edge 3D technology platform for custom ASICs/SoCs from design through manufacturing, packaging, and test.
• Optimize digital blocks for performance, power, and area using physical design techniques.
• Define methodologies by investigating performance, power, and area across nodes and implementation techniques.
• Collaborate with PD, technology, circuits, and architecture teams and IP partners on advanced flows and TSV-based methods.

Skills

Physical design

3D integration

Team collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's or PhD preferred in Electrical/Computer Engineering or CS

Tools

Synopsys

Cadence

Siemens EDA / Mentor Graphics

Job description

Share Physical Design Engineer, 3D Technology

corporate_fare Google place Sunnyvale, CA, USA

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV).
• Experience running industry standard tools for chip design, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with Power, Performance, and Area (PPA) design trade-offs and optimizations in physical design spaces.
• Experience with advanced FinFET and gate-all-around (GAA) technology nodes, including enabling physical design flows in these nodes.
• Experience delivering optimized digital place-and-route blocks leading to product tapeouts.
• Experience with programming/scripting (e.g., TCL, Python, or Perl) for design flow automation.
• Understanding of standard cells, SRAMs, power, noise, and IR analysis.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Physical Design Engineer, 3D Technology you will collaborate with technology, physical design, circuit design, and hardware architecture teams to overcome the slowing of Moore’s Law while delivering cutting edge ASIC’s and SoC’s. You will help develop new 3D technology physical design methodologies to drive best product PPA by optimizing across technology, digital block implementation, clock distribution, floorplanning, circuits, memories, and third-party IPs.
You will drive new physical design flows that co-optimize across the entire design methodology space–including 3D–and see these through from inception to maturity and tapeout. This will include high impact physical design innovations with Through-Silicon Vias (TSVs) requiring methodology and verification flow development and ratification. As part of this work, you will participate in the development of exceptional technology in high performance computing and ensure product success.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Physical Design Engineer, 3D Technology you will collaborate with technology, physical design, circuit design, and hardware architecture teams to overcome the slowing of Moore’s Law while delivering cutting edge ASIC’s and SoC’s. You will help develop new 3D technology physical design methodologies to drive best product PPA by optimizing across technology, digital block implementation, clock distribution, floorplanning, circuits, memories, and third-party IPs.
You will drive new physical design flows that co-optimize across the entire design methodology space–including 3D–and see these through from inception to maturity and tapeout. This will include high impact physical design innovations with Through-Silicon Vias (TSVs) requiring methodology and verification flow development and ratification. As part of this work, you will participate in the development of exceptional technology in high performance computing and ensure product success.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google .

• Drive development of a leading edge 3D technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
• Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques.
• Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
• Work with our physical design, technology, circuits, and architecture teams plus IP partners in advanced CMOS nodes.
• Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.