Senior ASIC Physical Design Engineer

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google LLC in Sunnyvale, CA, USA seeks a Share Senior ASIC Physical Design Engineer to drive the PD of TPU blocks from RTL to GDSII. You will collaborate with RTL, DFT, floorplanning, and full-chip signoff teams to optimize power, performance, and area while evaluating new micro-architectures and practical logic solutions.

The role requires working closely with external partners on PD closure and understanding STA, timing corners, derates, and PnR flows using Synopsys/Cadence tools.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 7 years of experience with physical design from RTL to GDSII, including floorplanning, place & route, timing closure.
• Experience in Python, Tcl, or Perl scripting.

Responsibilities

• Participate in the physical design of complex blocks and full-chip integration from RTL to GDSII.
• Collaborate with RTL, DFT, Floorplan, and Signoff teams to optimize PPA.
• Work with internal/external teams to achieve PD closure and timing objectives.

Skills

Physical design

Scripting (Python/Tcl/Perl)

RTL-to-GDSII knowledge

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Synopsys/Cadence PnR tools

Backend flows: DRC/LVS/PI/SI/LEC

DFT: Scan/MBIST/LBIST

Job description

Share Senior ASIC Physical Design Engineer

Google Sunnyvale, CA, USA

In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 7 years of experience with physical design (e.g., from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
• Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

• Experience working with external partners on physical design (PD) closure.
• Experience in static timing analysis (STA), with an understanding of how to define timing corners, margins and derates.
• Experience with Synopsys/Cadence PnR tools.
• Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
• Understanding of DFT including Scan, MBIST and LBIST.
• Understanding of performance, power and area (PPA) trade-offs.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full‑chip Signoff teams. Additionally, you will solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

• Participate in the physical design of complex blocks.
• Contribute to the design and closure of the full chip and individual blocks from RTL‑to‑GDS.
• Collaborate with internal logic and internal and external teams to achieve the best power/performance analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.