Physical Design Engineer, FullChip/ASIC Implementation

Google Inc.; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google Inc. is seeking a Mid-level Physical Design Engineer in Mountain View, CA to drive ASIC RTL2GDS implementation with focus on high performance, power, and area. You will work with cross-functional teams to deliver top-tier silicon features and optimizations for Google's products.

The role requires a Bachelor's in Electrical Engineering, 4 years in physical design, and hands-on experience with synthesis/PnR flows. Strong Verilog/SystemVerilog and scripting skills are highly valued.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 4 years of experience in physical design.
• Experience with synthesis/PnR tools (Genus, Innovus, DC, ICC) and sign-off convergence.

Responsibilities

• Develop ASIC RTL2GDS implementation for high-Performance, Power, Area (PPA).
• Define schemes to improve performance and power.
• Collaborate with cross-functional teams to deliver high-quality results.

Skills

Physical design

Synthesis & PnR

Sign-off convergence

Verilog/SystemVerilog

Tcl/Perl scripting

Education

Bachelor's degree in Electrical Engineering

Tools

Genus

Innovus

DC

ICC

Job description

Physical Design Engineer, FullChip/ASIC Implementation

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Google place Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in physical design.
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

Preferred qualifications:

• Experience in top-level floorplanning and block integration.
• Experience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.
• Experience with ASIC design flows and methodology of physical design.
• Understanding of circuit design, device physics, and deep submicron technology.
• Knowledge of Verilog/SystemVerilog and fundamentals of computer architecture.
• Effective skills with scripting languages such as Tcl, or Perl.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Define and implement innovative schemes to improve performance and power.
• Work with cross-functional teams to deliver best quality of results.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.