CPU Implementation Engineer for High-Performance Silicon

Apple Inc.; Santa Clara (CA); On-site; USD 129,300 - 194,700; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock plan

Tuition reimbursement

Job summary

Apple Inc. is seeking a CPU Implementation Engineer in Santa Clara, CA to drive micro-architecture decisions and deliver block-level CPU designs.

You will work with micro-architects to optimize power, performance and area, and push RTL-to-GDS convergence through synthesis and PnR techniques. The role involves collaboration with CAD/PD teams, top-level floorplanning, timing, and memory macro optimization to improve silicon yield and efficiency.

Qualifications

• Experience with TCL or Perl.
• Strong knowledge of digital logic design and circuits.
• Familiarity with high-performance CPU microarchitecture.
• Experience using industry-standard synthesis, PnR, STA and power analysis tools.

Responsibilities

• Define micro-architecture with micro-architects and support PPA trade-offs.
• Drive RTL-to-GDS design convergence via RTL optimizations for PPA.
• Deliver block-level design and backend closure including silicon yield improvements.
• Collaborate with CAD/PD teams on tool features and adoption in CPU design.
• Coordinate with cross-functional teams on floorplanning, timing, power, reliability and testability.
• Define and co-optimize memory macros and standard cells for PPA improvements.

Skills

TCL

Perl

Team work

Communication

Tools

Synthesis tools

Place-and-route (PnR)

STA tools

Floorplanning

Job description

Apple Inc. is seeking a CPU Implementation Engineer in Santa Clara, CA to drive micro-architecture decisions and deliver block-level CPU designs.

You will work with micro-architects to optimize power, performance and area, and push RTL-to-GDS convergence through synthesis and PnR techniques. The role involves collaboration with CAD/PD teams, top-level floorplanning, timing, and memory macro optimization to improve silicon yield and efficiency.