CPU Gate Level Synthesis Engineer

Apple Inc.

Santa Clara (CA)

On-site

USD 184,700 - 324,800

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Job summary

Apple's Silicon Engineering Group (SEG) is seeking a CPU Gate Level Synthesis Engineer to drive early-stage development of high-performance, low-power CPUs. You will run RTL to gate-level synthesis and seek opportunities to optimize timing, power, and area while collaborating across RTL, physical design and DFT teams.

The role requires a BS and 10+ years in digital logic, RTL synthesis and physical design, with preferred CPU implementation experience and scripting skills in Tcl, Perl or Python.

Qualifications

  • BS degree with 10+ years of relevant industry experience.
  • Experience in digital logic design, RTL synthesis, and physical design.
  • CPU implementation experience is a plus.

Responsibilities

  • Early RTL health assessment to detect potential timing/gate-depth issues and collaborate with RTL and physical design teams.
  • Early stage power estimation and validation for new micro-architectural features.
  • Enhance synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback.
  • Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow.
  • Partner with timing team to enable constraints generation at top levels.
  • Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs.
  • Track and analyze PPA trends through project cycle.

Skills

Digital logic design
RTL synthesis
Physical design
CPU implementation experience
Tcl scripting
Perl scripting
Python scripting
Cross-functional collaboration

Education

Bachelor's degree

Tools

Tcl
Perl
Python

Job description

Santa Clara, California, United States Hardware

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!Apple’s Silicon Engineering Group (SEG) is looking for a hardworking engineer for our CPU Gate Level Synthesis role to assess and optimize design quality. In this role, the candidate would be a part of Apple’s industry-leading CPU design team, working in a multi-functional role to ensure that our CPUs meet the highest standards for performance, power and area.

Description

As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running RTL to gate level synthesis and finding opportunities to optimize timing, power, and area for micro-architectural features. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, RTL optimization and power analysis.

Responsibilities
  • Early RTL health assessment to detect potential timing/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions
  • Early stage power estimation and validation for new micro-architectural features
  • Enhancing synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback
  • Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow
  • Partner with timing team to enable constraints generation at top levels
  • Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs
  • Track and analyze PPA trends through project cycle
Minimum Qualifications
  • Minimum BS and 10+ years of relevant industry experience
  • Experience in digital logic design, RTL synthesis, and physical design
Preferred Qualifications
  • The ideal candidate should possess CPU implementation experience
  • Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimization
  • Strong problem-solving, debugging, and collaboration skills in a fast-paced environment

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace.

Learn about reasonable accommodations for job applicants.

Apple accepts applications to this posting on an ongoing basis.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Physical Synthesis CAD Engineer
Physical Synthesis CAD Engineer

Apple • Austin (TX)

On-site
USD 147,000 - 273,000
Comprehensive medical and dental coverage
Retirement benefits
Employee stock purchasing options
+2
CPU Implementation Engineer
CPU Implementation Engineer

Apple Inc. • Santa Clara (CA)

On-site
USD 129,000 - 195,000
Medical and dental coverage
Retirement benefits
Employee stock plan
+1
CPU Silicon Validation Engineer
CPU Silicon Validation Engineer

Apple Inc. • Santa Clara (CA)

On-site
USD 137,000 - 187,000
CPU Processor Performance Verification Engineer
CPU Processor Performance Verification Engineer

Apple Inc. • Santa Clara (CA)

On-site
USD 129,000 - 195,000
CPU Microarchitect/RTL Engineer - Fetch, Out of Order
CPU Microarchitect/RTL Engineer - Fetch, Out of Order

Apple Inc. • Santa Clara (CA)

On-site
USD 150,000 - 278,000
Medical & dental
Stock programs
Tuition reimbursement
+1
CPU Implementation Engineer
CPU Implementation Engineer

Apple Inc. • Beaverton (OR)

On-site
USD 130,000 - 160,000
ASIC Design Manager
ASIC Design Manager

Apple Inc. • Cupertino (CA), Northern (KY)

Hybrid
USD 206,000 - 356,000
Stock plans
Retirement benefits
Education reimbursement
+1
Silicon Prototyping Engineer
Silicon Prototyping Engineer

Apple • Cupertino (CA)

On-site
USD 126,000 - 191,000
Comprehensive medical and dental coverage
Retirement benefits
Discounted products and services
+2
CPU Design Timing Engineer
CPU Design Timing Engineer

Apple • Beaverton (OR)

On-site
USD 181,000 - 319,000
Comprehensive medical and dental coverage
Retirement benefits
Employee stock purchase plan
+2
CPU Implementation Engineer
CPU Implementation Engineer

Apple Inc. • Austin (TX)

On-site
USD 120,000 - 180,000