CPU Architecture Verification Engineer - Architect Correctness

NUVACORE; Santa Clara (CA); Presencial; USD 170.000 - 230.000; Jornada completa

Descripción de la vacante

NUVACORE in Santa Clara, CA is seeking Verification Engineers at multiple levels—from Senior Engineer to Principal—to help prove that the NUVACORE CPU is architecturally correct. Join the design verification team to drive architectural verification, build stimuli, and develop flows that catch bugs long before silicon.

You will create verification environments, run co-simulation against a golden model, and work with architects and RTL to root‑cause mismatches, support emulation, FPGA, and silicon

Formación

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design‑verification experience, ideally on a CPU or complex digital design.
• Strong knowledge of CPU architecture and micro‑architecture — the instruction set, architectural state, exceptions, and privilege model — with a good understanding of at least one modern ISA (x86, ARM, or RISC‑V).
• Hands‑on functional verification: test plans, testbenches, checkers, and coverage.
• Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
• Experience writing and debugging tests in assembly for CPU verification.

Responsabilidades

• Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.
• Environment Setup: Build, maintain, and scale robust verification environments — including co‑simulation against the golden reference model — that compare architectural state end to end.
• Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
• Cross-functional Collaboration: Partner with architects and RTL teams to root‑cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring‑up.

Conocimientos

CPU architecture

Micro-architecture

C/C++/Rust

SystemVerilog

Python

Testbenches & coverage

Assembly testing

Educación

Electrical/Computer Engineering

Descripción del empleo

NUVACORE in Santa Clara, CA is seeking Verification Engineers at multiple levels—from Senior Engineer to Principal—to help prove that the NUVACORE CPU is architecturally correct. Join the design verification team to drive architectural verification, build stimuli, and develop flows that catch bugs long before silicon.

You will create verification environments, run co-simulation against a golden model, and work with architects and RTL to root‑cause mismatches, support emulation, FPGA, and silicon