Senior SoC DFT Engineer | ATPG/MBIST/JTAG Expert

MaziCTools; United States; À distance; USD 120 000 - 170 000; Plein temps

Résumé du poste

Apple Beaverton, Oregon is seeking a seasoned SoC DFT Engineer to lead architecture and implementation of DFT for next-generation chips. You will verify DFT in simulation, develop ECOs with the DV team, and work across STA, physical, power and logic teams to ensure robust silicon.

The role demands deep knowledge of ATPG, JTAG, MBIST and industry DFT standards, with hands-on scripting and debugging of waveform data. You will coordinate test vectors on silicon and drive multi-engineering schedules.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Knowledge of DFT standards (ATPG, JTAG, MBIST) and trade-offs between test quality and test time.
• Experience with Verilog and/or VHDL and simulators; debugging waveform data.
• Knowledge of industry standards for DFT and design tools.
• Proven understanding of DV methodologies for validating DFT in simulation pre-silicon.

Responsabilités

• Developing and implementing DFT architecture.
• Implementing DFT infrastructure.
• Working with the DV team to verify DFT implementations and ECOs.
• Generating structural test vectors and analyzing/ improving coverage.
• Collaborating with designers on STA, physical, power and logical issues.
• Bringing up test vectors on silicon with test engineers.
• Running schedules and supporting multi-functional engineering efforts.

Connaissances

DFT architecture

Verilog

VHDL

DFT verification

Scripting

STA analysis

MBIST/JTAG

Formation

BS in Electrical Engineering

Outils

Verilog simulators

Waveform debugging tools

DFT design tools

Description du poste

Apple Beaverton, Oregon is seeking a seasoned SoC DFT Engineer to lead architecture and implementation of DFT for next-generation chips. You will verify DFT in simulation, develop ECOs with the DV team, and work across STA, physical, power and logic teams to ensure robust silicon.

The role demands deep knowledge of ATPG, JTAG, MBIST and industry DFT standards, with hands-on scripting and debugging of waveform data. You will coordinate test vectors on silicon and drive multi-engineering schedules.