Senior Principal DFT & Test Engineer (MBIST, ATPG, JTAG)

Ampere; Santa Clara (CA); On-site; USD 237,000 - 356,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401K retirement plan

Unlimited flextime

Paid holidays

Job summary

Ampere is seeking a highly skilled engineer to design, implement, and verify DFT features for next-generation server-class processors. You will collaborate with global teams to deliver robust test solutions and drive post-silicon bring-up activities.

The role requires strong Verilog HDL, MBIST/EDT/SSN expertise, and hands-on experience with ATE data, as well as proficiency in major EDA tool flows from Mentor, Cadence, and Synopsys.

Qualifications

• Experience designing and verifying DFT features for high-end processors.
• Hands-on MBIST, boundary scan, JTAG/IJTAG in advanced nodes.
• Proficient in Verilog HDL and debugging tools.
• Experience with ATE patterns and post-silicon bring-up.
• Ability to work with Mentor, Cadence, Synopsys tool flows.

Responsibilities

• Collaborate with global teams to design, implement and verify DFT features.
• Develop ATE patterns and support post-silicon bring-up and debugging.
• Perform RTL/gate-level simulations and waveform debugging.
• Lead test plans and coverage analysis for DFT and MBIST.

Skills

Verilog HDL

MBIST

DFT

Test planning

Scripting (Perl/Tcl)

Python

JTAG/IJTAG

Education

Electrical or Computer Engineering degree

Bachelor’s/Master’s/PhD with years experience

Tools

Siemens Tessent

Synopsys SMS/SHS

Mentor Graphics

Cadence

Job description

Ampere is seeking a highly skilled engineer to design, implement, and verify DFT features for next-generation server-class processors. You will collaborate with global teams to deliver robust test solutions and drive post-silicon bring-up activities.

The role requires strong Verilog HDL, MBIST/EDT/SSN expertise, and hands-on experience with ATE data, as well as proficiency in major EDA tool flows from Mentor, Cadence, and Synopsys.