Lead Micro-Architect — Coherent Interconnect & LLC

Samsung Electronics America; San Jose (CA); On-site; USD 222,000 - 365,000; Full time

Benefits offered by this job

Medical, dental, vision insurance

401(k)

Free onsite lunch

Tuition assistance

Paid time off

Wellness incentives

Job summary

Samsung Electronics America is seeking a Principal Micro-architect to lead microarchitecture development for coherent interconnect IP and LLC blocks used in high-performance devices. You will own RTL design, optimization, and timing closure, collaborating with system architects to refine architectures and drive validation across teams.

You have deep Verilog/SystemVerilog expertise, memory subsystem knowledge, and experience guiding engineers through design flows and verification.

Qualifications

• Strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs.
• Demonstrated experience spanning architecture definition through RTL implementation.
• Familiarity with on-chip network topologies and AMBA protocols (CHI/ACE/AXI).
• Deep expertise in Verilog/SystemVerilog and full ASIC design flow (STA, DFT, ECO).
• Strong memory subsystem and cache design knowledge with coherence mechanisms.

Responsibilities

• Lead microarchitecture development for coherent interconnect IP and LLC blocks.
• Drive RTL design, performance and power optimization, and timing closure.
• Collaborate with system architects to define next-generation architectures.
• Mentor junior engineers and coordinate with verification, physical design, and CAD teams.

Skills

RTL design

Coherent interconnect

LLC design

Verilog/SystemVerilog

AMBA5 CHI

AMBA4 ACE

AXI

Memory subsystem

Leadership

Python

Education

Bachelor's degree in CS/CE

Master's degree

PhD

Job description

Samsung Electronics America is seeking a Principal Micro-architect to lead microarchitecture development for coherent interconnect IP and LLC blocks used in high-performance devices. You will own RTL design, optimization, and timing closure, collaborating with system architects to refine architectures and drive validation across teams.

You have deep Verilog/SystemVerilog expertise, memory subsystem knowledge, and experience guiding engineers through design flows and verification.