Lead Micro-Architect, Coherent Interconnect IP

Bzpp; United States; On-site; USD 222,000 - 365,000; Full time

Job summary

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are assembling a high-caliber team to advance coherent interconnect IP and LLC blocks for next-generation devices. The Principal Micro-architect will lead architecture definition, RTL implementation, and PPA optimization across multi-disciplinary teams.

The role demands deep expertise in Verilog/SystemVerilog, on-chip interconnect protocols, and experience driving end-to-end design from architectural

Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering or related field, or 13+ years with a Master’s, or 11+ years with a PhD.
• Strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs.
• Familiarity with on-chip network topologies and coherent interconnect protocols.
• Deep expertise in Verilog/SystemVerilog and ASIC design flow including STA/DFT/ECO.

Responsibilities

• Lead microarchitecture development of custom coherent interconnect IP and LLC blocks for next-generation designs.
• Drive RTL design, performance and power optimization, and timing closure.
• Collaborate with system architects to define architectures and with verification for correctness.
• Develop high-quality RTL implementations meeting PPA goals.
• Mentor junior engineers and work with cross-functional teams.

Skills

RTL design

On-chip interconnect

Verilog/SystemVerilog

Memory subsystem architecture

Coherent interconnect protocols

Architecture definition

Scripting (Perl/Python)

Mentoring engineers

Education

Bachelor's degree in Computer Science/Computer Engineering

Master's degree in Computer Science/Computer Engineering

PhD in relevant field

Job description

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are assembling a high-caliber team to advance coherent interconnect IP and LLC blocks for next-generation devices. The Principal Micro-architect will lead architecture definition, RTL implementation, and PPA optimization across multi-disciplinary teams.

The role demands deep expertise in Verilog/SystemVerilog, on-chip interconnect protocols, and experience driving end-to-end design from architectural